Dr. Azizi

Senior Lecturer


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Projects

This list is the projects under research grants which I currently participating in, as well as past projects that has been completed.


Open Topics for Master/PhD Candidates

Last update on 18/8/2017.


Simultaneous Exploration of Mapping and Routing on Hard Real-Time Embedded Networks-On-Chip

Networks-On-Chip (NoC) is seen as a new network paradigm for addressing the limitation of the current bus-based communication in multi-core embedded systems. Some of these systems are designed for executing hard real-time services in flight and automotive controls. The main requirement of such systems dictates that not only the output must be correct, but also it must be delivered within strict deadline. Otherwise, loss of life may result, for example, from late activation of car airbag or brake systems. One of the main design goal for such systems is finding a schedulable task mapping to meet the hard real-time requirement. Although, the schedulable mapping has successfully been found with the static X-Y routing protocol, the impact of different routing schemes on the mapping is unknown. Since NoC is capable of implementing different routing schemes, the study on their impacts to the predictability of the systems cannot be ignored.


NoC Optimisation Function on FPGA Platform for Facilitating Validation of Mappings

Networks-On-Chip (NoC) is a new network paradigm for addressing the limitation of the current bus-based communication in multi-core embedded systems. Some of these systems are designed for executing hard real-time services in flight and automotive controls. At the early design stage, hardware and software complexity is reduced and hence a NoC mapping can be alter easily if it does not meet with the design objective. For this purpose, metaheuristics are efficient in finding the mapping at the high-level of abstraction. However, as the fitness function becomes more complex, its execution time becomes slow. There is a need to accelerate this function so that the mapping heuristic remains efficient in exploring many alternatives. Based on the FPGA-based NoC model implementation and fitness function how efficient the validation process of mapping becomes will be studied.


Security-Aware Mapping on Hard Real-Time Embedded Networks-On-Chip

Networks-On-Chip (NoC) is seen as a new network paradigm for addressing the limitation of the current bus-based communication in multi-core embedded systems. Some of these systems are designed for executing hard real-time services in flight and automotive controls. The main requirement of such systems dictates that not only the output must be correct, but also it must be delivered within strict deadline. Otherwise, loss of life may result, for example, from late activation of car airbag or brake systems. One of the main design goal for such systems is finding a schedulable task mapping to meet the hard real-time requirement. Although, the schedulable mapping has successfully been found, the impact of mapping to security is still unknown. Since NoC is capable of implementing different mapping, the study on their impacts to the predictability of the systems cannot be ignored. The existing evolutionary exploration technique will be improved in a way that the exploration of mapping is able to meet the hard real-time and security requirements


Undegraduate Projects

Kindly visit here for open final year projects.

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